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| IRFF310 Data Sheet March 1999 File Number 1888.3 1.35A, 400V, 3.600 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits. Formerly developmental type TA17444. Features * 1.35A, 400V * rDS(ON) = 3.600 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRFF310 PACKAGE TO-205AF BRAND IRFF310 Symbol D NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFF310 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFF310 400 400 1.35 5.5 20 15 0.12 150 -55 to 150 300 260 UNITS V V A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and StorageTemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured from the Drain Lead, 5mm (0.2in) from Header to Center of Die Measured from the Source Lead, 5mm (0.2in) from Header and Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device Inductances D LD G LS S TEST CONDITIONS VGS = 0V, ID = 250A (Figure 10) VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VGS = 20V VGS = 10V, ID = 0.8A (Figures 8, 9) VDS, = 10V, ID = 1.2A (Figure 12) VDD 0.5 x Rated BVDSS, RG = 9.1, ID 1.35A, RL = 144.5 for BVDSS = 400V, RL = 126 for BVDSS = 350V (Figures 17, 18), MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID = 1.35A, VDS = 0.8 x Rated BVDSS , Ig(REF) = 1.5mA (Figures 14, 19, 20), Gate Charge is Essentially Independent of Operating Temperature MIN 400 2.0 1.35 1.0 - TYP 3.3 1.2 3 10 5 8 6 3 3 135 35 8 5.0 MAX 4.0 25 250 100 3.600 10 20 10 15 7.5 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero-Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse-Transfer Capacitance Internal Drain Inductance VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - Internal Source Inductance LS - 15 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA Free Air Operation - - 8.33 175 oC/W oC/W 2 IRFF310 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier G D MIN - TYP - MAX 1.35 5.5 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES: VSD trr QRR TJ = 25oC, ISD = 1.35A, VGS = 0V (Figure 13) TJ = 150oC, ISD = 1.35A, dISD/dt = 100A/s TJ = 150oC, ISD = 1.35A, dISD/dt = 100A/s - 380 2.7 1.6 - V ns C 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 40V, start TJ = 25oC, L = 44.89H, RG = 50, peak IAS = 1.35A (See Figures 15, 16). Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 TC = 25oC, Unless Otherwise Specified 1.6 1.4 ID, DRAIN CURRENT (A) 1.2 1.0 0.8 0.6 0.4 0.2 0 25 50 75 100 125 150 0.8 0.6 0.4 0.2 0 0 50 100 150 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 ZJC , NORMALIZED THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 0.1 10-3 10-2 t1, RECTANGULAR PULSE DURATION (LC) t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 1 10 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 IRFF310 Typical Performance Curves 50 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) TC = 25oC, Unless Otherwise Specified 10 (Continued) VGS = 9V 8 VGS = 10V VGS = 8V 80s PULSE TEST ID, DRAIN CURRENT (A) 10 10ms 100ms 1 1ms 10s 100s DC VGS = 7V 6 4 VGS = 6V 0.1 0.05 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 2 VGS = 5V VGS = 4V 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 1000 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 5 VGS = 10V VGS = 9V VGS = 8V ID(ON) , ON-STATE DRAIN CURRENT (A) 80s PULSE TEST 4 5 TJ = 175oC 4 TJ = 25oC TJ = -55oC VDS > ID(ON) x rDS(ON) MAX 80s PULSE TEST 2 ID, DRAIN CURRENT (A) 3 3 VGS = 7V VGS = 6V 2 1 VGS = 5V VGS = 4V 0 1 2 3 4 VDS , DRAIN TO SOURCE VOLTAGE (V) 5 1 0 0 0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 4 2s PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE 2.2 VGS = 10V ID = 5.6A 1.8 3 VGS = 10V 1.4 2 1.0 1 VGS = 20V 0.6 0 0 2 4 6 ID, DRAIN CURRENT (A) 8 10 0.2 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4 IRFF310 Typical Performance Curves 1.15 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A TC = 25oC, Unless Otherwise Specified 400 (Continued) VGS = 0V, f = 1MHz CISS = CGS + CGD C, CAPACITANCE (pF) CRSS = CGD 1.05 300 COSS CDS + CGS 0.95 200 CISS 100 COSS CRSS 0.85 0.75 -40 0 40 80 120 160 0 10 20 30 40 50 TJ , JUNCTION TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 80s PULSE TEST gfs , TRANSCONDUCTANCE (S) 2.0 TJ = -55oC TJ = 25oC ISD , SOURCE TO DRAIN CURRENT (A) 2.4 10 TJ = 175oC 1.6 TJ = 125oC 1.2 0.8 0.4 0 0 2 4 6 ID , DRAIN CURRENT (A) 8 10 1 TJ = 25oC 0.1 0 1 2 3 4 5 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS , GATE TO SOURCE VOLTAGE (V) ID = 4A VDS = 160V VDS = 100V VDS = 40V 15 10 5 0 0 2 4 6 8 10 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 IRFF310 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + - 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS 90% tOFF td(OFF) tf 90% + RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2F 50k 0.3F G DUT 0 Ig(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 6 IRFF310 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 7 |
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